Description

Today's greater than ever functionality of electronic devices is possible only by integrating an increasing number of highly complex tasks into the so called embedded systems on chip (SoC). According to "Moore's Law" the complexity of hardware systems doubles itself exponentially over time. This trend is still holding on, already enabling chips integrating one billion transistors. The required technology shrink - now below 65nm - rises the problem of dramatically increasing power consumption, especially in consequence of so called leakage currents.

One inevitable means for handling the exponentially increasing complexity in the domain of chip design and manufacturing is
Electronic Design Automation (EDA). EDA-tools aid the designer to meet requirements like timing, chip area, and with drastically increasing significance power consumption, all of these directly influencing product costs and the important time-to-market.

CLEAN (controlling leakage power in nanoCMOS SOC's) is an FP6-IST project, in which the problem of leakage currents in the upcoming technologies (65nm and below) is addressed. The project is funded by the European Union as a 3 year Integrated Project.